Schmitt Trigger RC Oscillator Calculator
Calculate a Schmitt-trigger inverter RC relaxation oscillator from explicit output levels and switching thresholds. The calculator solves high time, low time, period, frequency, output-high duty cycle, R/C values, normalized thresholds, and tolerance range.
OSC-008 models the fixed topology where the output drives the input node through a timing resistor and the input node has a capacitor to ground. It does not calculate comparator positive-feedback threshold networks.
Engineering tool
Schmitt Trigger RC Oscillator Calculator
Analyze a Schmitt-trigger inverter RC oscillator using explicit VOH, VOL, VT+, and VT- thresholds.
Calculation mode
Parameter panel
Result console
- Oscillation Frequency
- 721.348 Hz
- Period
- 1.38629 ms
- High Time
- 693.147 µs
- Low Time
- 693.147 µs
- Output High Duty
- 50%
- Hysteresis
- 1.66667V
- alpha+
- 0.666667
- alpha-
- 0.333333
- Timing Factor K
- 1.38629
- High End R Current
- 16.6667µA
- Low End R Current
- 16.6667µA
- Feasibility
- Feasible
Real Schmitt thresholds vary with device family, supply voltage, process, and temperature; typical values are not guaranteed limits. This model uses explicit thresholds and does not calculate comparator positive-feedback hysteresis networks.
Formula audit
| Adopted Topology | Schmitt-trigger inverter output drives R; R connects to the input node; C connects from input node to ground. |
|---|---|
| R Connection | R is the output-to-input timing resistor. |
| C Connection | C is the input-node timing capacitor to ground. |
| Output Node | The displayed duty cycle is output-high duty cycle. |
| VOH Definition | VOH is the high output level used as the capacitor charging target. |
| VOL Definition | VOL is the low output level used as the capacitor discharging target. |
| VT+ Definition | VT+ is the upper input switching threshold. |
| VT- Definition | VT- is the lower input switching threshold. |
| High-Time Formula | tHIGH = RC ln[(VOH - VT-)/(VOH - VT+)]. |
| Low-Time Formula | tLOW = RC ln[(VT+ - VOL)/(VT- - VOL)]. |
| Period Formula | T = tHIGH + tLOW = RC K. |
| Frequency Formula | f = 1 / (RC K). |
| Timing Factor K | K is the sum of the two logarithmic threshold factors. |
| Feasibility Conditions | VOL < VT- < VT+ < VOH. |
| Symmetric Threshold Formula | alpha- = beta and alpha+ = 1 - beta gives tHIGH = tLOW. |
| 1/3-2/3 Special Case | Only for beta = 1/3, f = 1/(2RC ln2) ≈ 0.721347/(RC). |
| Tolerance Model | R/C corners are evaluated; optional voltage corners are enumerated and invalid corners counted. |
| Formula Used | 721.348 Hz from 100 kΩ and 10 nF. |
Formula reference
Schmitt Trigger RC Oscillator Formulas
The adopted model is a Schmitt-trigger inverter with R from output to input and C from input to ground. The capacitor charges toward VOH and discharges toward VOL.
tHIGH = RC ln[(VOH - VT-) / (VOH - VT+)]tLOW = RC ln[(VT+ - VOL) / (VT- - VOL)]T = tHIGH + tLOWf = 1 / TD = tHIGH / TK = ln[(VOH - VT-) / (VOH - VT+)] + ln[(VT+ - VOL) / (VT- - VOL)]R = 1 / (f C K)C = 1 / (f R K)VOL < VT- < VT+ < VOHSymmetric: T = 2RC ln[(1 - beta) / beta]Variable definitions
- R
- output-to-input timing resistor
- C
- input-node timing capacitor
- VOH
- high output voltage
- VOL
- low output voltage
- VT+
- upper switching threshold
- VT-
- lower switching threshold
- D
- output-high duty cycle
Schmitt Trigger RC Formula Audit
| Adopted Topology | Schmitt-trigger inverter output connected through R to the input node, with C from input node to ground. |
|---|---|
| High-Time Formula | tHIGH = RC ln[(VOH - VT-)/(VOH - VT+)]. |
| Low-Time Formula | tLOW = RC ln[(VT+ - VOL)/(VT- - VOL)]. |
| Period Formula | T = tHIGH + tLOW. |
| Frequency Formula | f = 1/T = 1/(RC K). |
| Duty-Cycle Definition | D is output-high duty cycle, D = tHIGH/T. |
| Timing Factor K | K is the sum of the high-time and low-time logarithmic factors. |
| Feasibility Conditions | VOL < VT- < VT+ < VOH. |
| Symmetric Threshold Formula | VT- = VOL + beta(VOH - VOL), VT+ = VOL + (1 - beta)(VOH - VOL). |
| 1/3-2/3 Special Case | For beta = 1/3, T = 2RC ln2 and f ≈ 0.721347/(RC). |
| Tolerance Model | R/C min/max and optional voltage-threshold corners are evaluated directly. |
| Propagation Delay Boundary | Real gate propagation delay is not included in the ideal RC timing formula. |
Worked Examples
High time
Known: R = 100 kΩ, C = 10 nF, VOH = 5 V, VOL = 0 V, VT- = 5/3 V, VT+ = 10/3 V
tHIGH = RC ln2 ≈ 0.693147 ms.
Low time
Known: Same symmetric threshold case
tLOW = RC ln2 ≈ 0.693147 ms.
Period
Known: Same 100 kΩ / 10 nF case
T ≈ 1.386294 ms.
Frequency
Known: T ≈ 1.386294 ms
f ≈ 721.347 Hz.
Duty cycle
Known: Symmetric 1/3 and 2/3 thresholds
Output-high duty cycle is 50%.
Asymmetric thresholds
Known: VOH = 5 V, VOL = 0 V, VT- = 1 V, VT+ = 3 V
tHIGH and tLOW are different because the charge and discharge ratios differ.
Asymmetric duty
Known: Same 1 V / 3 V thresholds
Duty is not 50%, even with the same R and C.
Solve R
Known: Target = 1 kHz, C = 10 nF, symmetric 1/3-2/3 thresholds
R = 1/(f C 2ln2), then analyze returns about 1 kHz.
Solve C
Known: Target = 1 kHz, R known
C = 1/(f R K), then analyze returns the target frequency.
Invalid upper threshold
Known: VT+ >= VOH
Rejected because the capacitor cannot charge beyond the upper threshold.
Invalid lower threshold
Known: VT- <= VOL
Rejected because the capacitor cannot discharge below the lower threshold.
Invalid ordering
Known: VT- >= VT+
Rejected as a non-oscillating ideal threshold set.
Resistance scaling
Known: R doubled, thresholds fixed
Frequency is halved.
Capacitance scaling
Known: C doubled, thresholds fixed
Frequency is halved.
RC reciprocal scaling
Known: R doubled and C halved
Frequency is unchanged.
Duty invariance
Known: Change R or C only
Duty cycle is unchanged when thresholds stay fixed.
Capacitance unit consistency
Known: 1000 nF = 1 µF
Both entries produce the same timing result.
Resistance unit consistency
Known: 1000 kΩ = 1 MΩ
Both entries produce the same timing result.
Tolerance range
Known: R ±1%, C ±5%
fmin < fnominal < fmax.
Invalid voltage corner
Known: A threshold corner violates ordering
Corner is counted as invalid instead of silently ignored.
Engineering Notes
| Schmitt trigger oscillator | The circuit repeatedly charges and discharges a capacitor between two switching thresholds. |
|---|---|
| RC relaxation oscillator | The waveform is set by exponential RC motion, not by a sine-wave phase-shift condition. |
| Hysteresis | VT+ and VT- must be separated to define the charge and discharge endpoints. |
| VOH / VOL | Real output levels may not equal the supply rails, especially under load. |
| Duty cycle | Asymmetric thresholds or output swing can produce a duty cycle other than 50%. |
| Threshold variation | Datasheets often specify min, typical, and max thresholds; typical thresholds do not guarantee frequency. |
| Propagation delay | At high frequency, gate delay adds to ideal RC timing. |
| Input leakage | Large R values make leakage current and PCB contamination more important. |
| Parasitic capacitance | Gate input capacitance, PCB capacitance, and probe capacitance add to the intended timing capacitor. |
| Output resistance | Finite output resistance changes the effective charge and discharge resistance. |
| Comparator boundary | Comparator relaxation oscillators are related but usually derive thresholds from a feedback network. |
| Measurement | Probe loading can significantly change timing at a high-impedance RC node. |
Common Mistakes
- Using f = 1/(RC) without threshold factors.
- Treating 0.7213/(RC) as universal.
- Assuming every Schmitt device uses 1/3 and 2/3 VCC thresholds.
- Assuming VOH = VCC and VOL = 0 under all conditions.
- Ignoring the difference between VT+ and VT-.
- Reversing tHIGH and tLOW definitions.
- Confusing input-node duty with output-high duty.
- Calculating when VT+ is greater than or equal to VOH.
- Calculating when VT- is less than or equal to VOL.
- Ignoring propagation delay at high frequency.
- Ignoring leakage with very large R.
- Ignoring parasitic capacitance with very small C.
- Using typical thresholds as guaranteed frequency limits.
- Confusing Schmitt-trigger oscillator scope with comparator hysteresis design.
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Support reference
FAQ
What is a Schmitt-trigger RC oscillator?
It is a relaxation oscillator where a Schmitt-trigger inverter repeatedly charges and discharges an RC timing capacitor between lower and upper input switching thresholds.
How do I calculate its frequency?
Calculate tHIGH and tLOW from the exponential RC transitions, add them to get period T, then use f = 1/T.
Why are two switching thresholds required?
The two thresholds create hysteresis. Without separate upper and lower thresholds the input could chatter near one switching point instead of forming a clean relaxation cycle.
How do I calculate the high time?
For the adopted inverter topology, tHIGH = RC ln[(VOH - VT-)/(VOH - VT+)].
How do I calculate the low time?
For discharge toward VOL, tLOW = RC ln[(VT+ - VOL)/(VT- - VOL)].
How do I calculate duty cycle?
The output-high duty cycle is D = tHIGH / (tHIGH + tLOW), usually expressed as a percentage.
Why is there not one universal Schmitt oscillator frequency formula?
The timing depends on VOH, VOL, VT+ and VT-. Different logic families and supply voltages have different thresholds.
When can I use 0.7213 divided by RC?
Only for the ideal symmetric threshold case where VOL = 0, VOH is the high rail, VT- = VOH/3 and VT+ = 2VOH/3.
Are Schmitt thresholds always one-third and two-thirds of VCC?
No. That ratio is a useful ideal example, not a universal property of 74HC14, 74HCT14, CD40106 or other devices.
How do I choose R for a target frequency?
With known C and threshold levels, calculate K from the logarithmic timing factors and solve R = 1/(fCK).
How do I choose C for a target frequency?
With known R and threshold levels, solve C = 1/(fRK).
How does threshold tolerance affect frequency?
Threshold variation changes the logarithmic timing factor K, so it must be evaluated by threshold corners rather than treated as a simple percentage.
When does propagation delay become important?
Propagation delay matters when RC timing becomes short compared with the gate delay and output transition time.
What is the difference between this and a comparator relaxation oscillator?
This calculator assumes an existing Schmitt-trigger gate with defined thresholds. A comparator relaxation oscillator usually calculates thresholds from an explicit positive-feedback network.
Engineering Disclaimer
This calculator provides ideal first-pass Schmitt-trigger RC timing estimates. Real devices require datasheet checks for threshold limits, propagation delay, input leakage, output resistance, supply range, temperature, loading, and layout-dependent parasitics.