Comparator Relaxation Oscillator Calculator
Calculate a comparator relaxation oscillator using an explicit positive-feedback hysteresis network and RC timing network. The calculator solves beta, VT+, VT-, hysteresis width, high time, low time, frequency, duty cycle, timing components, and tolerance corners.
OSC-009 is distinct from the Schmitt-trigger RC oscillator: this page calculates switching thresholds from R1, R2, VREF, VOH and VOL instead of assuming a Schmitt device with predefined thresholds.
Engineering tool
Comparator Relaxation Oscillator Calculator
Analyze comparator relaxation oscillator thresholds, positive-feedback ratio, RC timing, duty cycle, and tolerance range.
Calculation mode
Parameter panel
Result console
- Oscillation Frequency
- 1.23315 kHz
- Upper Threshold VT+
- 3V
- Lower Threshold VT-
- 2V
- Feedback Ratio beta
- 0.2
- Hysteresis Width
- 1V
- Threshold Midpoint
- 2.5V
- High Time
- 405.465 µs
- Low Time
- 405.465 µs
- Period
- 810.93 µs
- Output High Duty
- 50%
- Timing Factor K
- 0.81093
- Feasibility
- Feasible
Open-collector comparator VOH represents the effective high level after the pull-up network; pull-up dynamics are not simulated. Input common-mode range is not evaluated without a device-specific comparator datasheet.
Formula audit
| Adopted Topology | Comparator positive input is the hysteresis threshold node. Comparator negative input is the RC timing node. |
|---|---|
| Timing Input | VC is connected to the inverting input in this V1 topology. |
| Threshold Input | The non-inverting input is driven by output through R1 and VREF through R2. |
| R1 Definition | R1 connects comparator output to the threshold node. |
| R2 Definition | R2 connects VREF to the threshold node. |
| VREF Definition | VREF biases the hysteresis window and can shift duty cycle. |
| Feedback Ratio | beta = R2 / (R1 + R2). |
| Upper Threshold | VT+ = beta VOH + (1 - beta) VREF. |
| Lower Threshold | VT- = beta VOL + (1 - beta) VREF. |
| Hysteresis | VHYS = beta(VOH - VOL). |
| High-Time Formula | tHIGH = RT C ln[(VOH - VT-) / (VOH - VT+)]. |
| Low-Time Formula | tLOW = RT C ln[(VT+ - VOL) / (VT- - VOL)]. |
| Duty Definition | D is output-high duty cycle. |
| Symmetric Special Case | For ±V output and VREF = 0, T = 2RT C ln[(1 + beta)/(1 - beta)]. |
| Open-Collector Boundary | Pull-up rise time and output capacitance are not modeled. |
| Propagation-Delay Boundary | Comparator propagation delay and overdrive behavior are not included. |
| Common-Mode Boundary | Input common-mode validity must be checked separately. |
| Formula Used | 1.23315 kHz with beta 0.2. |
Formula reference
Comparator Relaxation Oscillator Formulas
The adopted topology drives the non-inverting comparator input from output through R1 and VREF through R2. The inverting input is the RC timing node.
VTH = (VOUT/R1 + VREF/R2) / (1/R1 + 1/R2)VTH = beta VOUT + (1 - beta)VREFVT+ = beta VOH + (1 - beta)VREFVT- = beta VOL + (1 - beta)VREFVHYS = beta(VOH - VOL)tHIGH = RT C ln[(VOH - VT-) / (VOH - VT+)]tLOW = RT C ln[(VT+ - VOL) / (VT- - VOL)]T = tHIGH + tLOWf = 1/TD = tHIGH/TRT = 1/(f C K)C = 1/(f RT K)Variable definitions
- R1
- resistor from comparator output to threshold node
- R2
- resistor from VREF to threshold node
- RT
- output-to-capacitor timing resistor
- C
- timing capacitor
- VOH / VOL
- effective output high and low levels
- VREF
- threshold bias reference
- beta
- R2/(R1 + R2)
Comparator Formula Audit
| Adopted Topology | Non-inverting comparator threshold node from output through R1 and VREF through R2; RC timing node on the inverting input. |
|---|---|
| Feedback Ratio | beta = R2/(R1 + R2). |
| Upper Threshold | VT+ = beta VOH + (1 - beta)VREF. |
| Lower Threshold | VT- = beta VOL + (1 - beta)VREF. |
| Hysteresis | VHYS = beta(VOH - VOL). |
| High-Time Formula | tHIGH = RT C ln[(VOH - VT-) / (VOH - VT+)]. |
| Low-Time Formula | tLOW = RT C ln[(VT+ - VOL) / (VT- - VOL)]. |
| Period / Frequency | T = tHIGH + tLOW and f = 1/T. |
| Duty Definition | D is output-high duty cycle. |
| Symmetric Case | For VOH = +V, VOL = -V and VREF = 0, T = 2RT C ln[(1 + beta)/(1 - beta)]. |
| Open-Collector Boundary | Entered VOH represents the effective high level after the pull-up network. |
| Common-Mode Boundary | Comparator input common-mode range is not evaluated by the ideal model. |
Worked Examples
Upper threshold
Known: VOH = 5 V, VOL = 0 V, VREF = 2.5 V, beta = 0.2
VT+ = 0.2 x 5 + 0.8 x 2.5 = 3.0 V.
Lower threshold
Known: Same network
VT- = 0.2 x 0 + 0.8 x 2.5 = 2.0 V.
Hysteresis
Known: VOH - VOL = 5 V, beta = 0.2
VHYS = 1.0 V.
Feedback ratio
Known: R1 = 40 kΩ, R2 = 10 kΩ
beta = R2/(R1 + R2) = 0.2.
High time
Known: RT = 100 kΩ, C = 10 nF, VT- = 2 V, VT+ = 3 V
tHIGH = RT C ln[(5 - 2)/(5 - 3)].
Low time
Known: Same threshold set
tLOW = RT C ln[(3 - 0)/(2 - 0)].
50% midpoint case
Known: VREF = 2.5 V with 0 V / 5 V output
The threshold window is centered and ideal duty is 50%.
Biased reference
Known: Move VREF away from midpoint
Thresholds shift and high/low times are no longer equal.
Solve RT
Known: Target 1 kHz, known C and threshold network
RT = 1/(f C K), then analyzer recovers about 1 kHz.
Solve C
Known: Target 1 kHz, known RT
C = 1/(f RT K), then analyzer recovers about 1 kHz.
Solve beta
Known: Desired hysteresis = 1 V, output span = 5 V
beta = 0.2.
Solve R2
Known: beta = 0.2, R1 = 40 kΩ
R2 = beta R1/(1 - beta) = 10 kΩ.
Solve R1
Known: beta = 0.2, R2 = 10 kΩ
R1 = R2(1 - beta)/beta = 40 kΩ.
Bipolar symmetry
Known: VOH = +5 V, VOL = -5 V, VREF = 0 V, beta = 0.25
VT+ = +1.25 V, VT- = -1.25 V and duty is 50%.
Symmetric closed form
Known: Same bipolar case
General timing equals T = 2RT C ln[(1 + beta)/(1 - beta)].
Tolerance
Known: R1/R2/RT ±1%, C ±5%
R1/R2 tolerance shifts beta and threshold range as well as timing.
RT scaling
Known: RT doubled
Frequency is halved.
Capacitance units
Known: 1000 nF = 1 µF
Both entries produce identical timing.
Resistor ratio round trip
Known: R1/R2 -> beta -> solved resistor
The original ratio is recovered.
Invalid beta
Known: beta <= 0 or beta >= 1
Rejected to avoid invalid hysteresis thresholds.
Engineering Notes
| Comparator relaxation oscillator | The circuit combines positive feedback thresholds with RC charging and discharging. |
|---|---|
| Positive feedback | R1 and R2 generate threshold movement as the output switches high and low. |
| Reference voltage | VREF sets the threshold midpoint and can intentionally bias duty cycle. |
| RC timing | RT and C set the time scale, while thresholds set the logarithmic timing factor. |
| Open collector | LM393-style outputs need a pull-up, and the pull-up affects the real high transition. |
| Propagation delay | Comparator delay and input overdrive behavior can affect high-frequency operation. |
| Common-mode range | The ideal thresholds still must be inside the comparator input common-mode range. |
| Op-amp substitution | Ordinary op-amps may recover slowly from saturation and are not always valid comparator replacements. |
| Tolerance | Feedback resistor tolerance changes beta, thresholds, frequency and duty cycle. |
| Parasitics | Comparator input capacitance, PCB capacitance and probe loading alter the effective timing capacitance. |
Common Mistakes
- Treating a comparator oscillator as the same thing as a Schmitt-gate oscillator.
- Forgetting to calculate thresholds from the positive-feedback network.
- Reversing the R1/R2 beta definition.
- Using a beta formula that does not match the schematic node naming.
- Assuming VOH equals VCC under load.
- Assuming VOL equals 0 V for every comparator.
- Ignoring VREF and threshold midpoint shift.
- Using only 1/(RC) for frequency.
- Calculating with invalid threshold ordering.
- Treating hysteresis width as threshold midpoint.
- Ignoring open-collector pull-up dynamics.
- Ignoring propagation delay and input overdrive.
- Ignoring comparator common-mode input range.
- Using an op-amp as a comparator without checking saturation recovery.
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Support reference
FAQ
What is a comparator relaxation oscillator?
It is an oscillator that combines comparator hysteresis with RC charging and discharging to create a square-wave output and a ramp-like timing voltage.
How do I calculate its oscillation frequency?
Calculate the upper and lower thresholds from the positive-feedback network, calculate tHIGH and tLOW from the RC exponential equations, then use f = 1/(tHIGH + tLOW).
How are the upper and lower thresholds calculated?
For the adopted topology, VT+ = beta VOH + (1 - beta)VREF and VT- = beta VOL + (1 - beta)VREF, where beta = R2/(R1 + R2).
How does the positive-feedback resistor ratio affect hysteresis?
The hysteresis width is VHYS = beta(VOH - VOL). Larger beta gives wider hysteresis and threshold points closer to the output rails.
How do I calculate comparator oscillator duty cycle?
Duty cycle is output-high time divided by total period: D = tHIGH/(tHIGH + tLOW).
Why is the frequency not just 1 divided by RC?
The logarithmic timing factor depends on VOH, VOL, VREF and beta, so there is no universal RC-only frequency constant.
How do I choose the timing resistor?
With known capacitance and thresholds, solve RT = 1/(f C K), where K is the total logarithmic timing factor.
How do I choose the timing capacitor?
With known RT and thresholds, solve C = 1/(f RT K).
How do I design the hysteresis width?
Use beta = VHYS/(VOH - VOL), then choose R1 and R2 so beta = R2/(R1 + R2).
How does reference voltage affect duty cycle?
Moving VREF shifts the threshold midpoint. If thresholds are no longer centered between VOL and VOH, high and low times can differ.
Can a comparator oscillator produce 50% duty cycle?
Yes, in the ideal model, symmetric thresholds around the output midpoint produce equal high and low times.
How do resistor tolerances affect frequency?
R1 and R2 tolerance change beta and therefore both thresholds. RT and C tolerance change the RC product directly.
How does propagation delay affect the oscillator?
At high frequency or very small hysteresis, comparator propagation delay and output transition time can dominate the ideal RC timing.
Can I use an op-amp instead of a comparator?
Not always. Many op-amps have slow saturation recovery, limited input behavior and output stages that make them poor comparator substitutes.
How does an open-collector comparator affect the circuit?
For open-collector outputs, VOH is set by the pull-up network and the high-going edge can be slowed by pull-up resistance and output capacitance.
Engineering Disclaimer
This calculator provides ideal first-pass comparator relaxation oscillator estimates. Real circuits require comparator datasheet checks for common-mode range, output swing, open-collector pull-up dynamics, propagation delay, input overdrive, loading, parasitic capacitance, and temperature behavior.