Digital Logic Calculators

PurposeGenerate truth tables, Boolean expressions, gate descriptions, comparisons, and custom input results for standard digital logic gates.

InputEngineering parameters

OutputCalculated result

PurposeEvaluate Boolean expressions, generate truth tables, compare equivalence, validate syntax, and inspect parsed expression structure.

InputEngineering parameters

OutputCalculated result

PurposeSimplify 2, 3, and 4 variable Boolean logic with Karnaugh maps, minterms, don't-care terms, Gray-code ordering, and verified SOP output.

InputMarking / Code

OutputDecoded value

PurposeCalculate fixed-width binary addition, subtraction, multiplication, division, carry, borrow, overflow, and signed or unsigned interpretation.

InputEngineering parameters

OutputCalculated result

PurposeConvert decimal integers to two's-complement binary, decode signed binary patterns, analyze signed ranges, detect overflow, and perform sign extension.

InputMarking / Code

OutputDecoded value

PurposeCalculate fixed-width binary AND, OR, XOR, NOT, shifts, masks, bit mutation, field extraction, and Hamming distance.

InputEngineering parameters

OutputCalculated result

PurposeConvert Binary-Reflected Gray Code, generate bounded sequence windows, and analyze adjacent state transitions.

InputMarking / Code

OutputDecoded value

PurposeAnalyze SR, JK, D, and T flip-flop next states, characteristic tables, excitation tables, and ideal clock-edge sequences.

InputEngineering parameters

OutputCalculated result

PurposeCalculate required flip-flops, counter modulus, maximum states, unused states, wraparound behavior, cascaded counters, and Mod-N design comparisons.

InputEngineering parameters

OutputCalculated result

PurposeCalculate digital clock divider ratios, output frequency, output period, counter bits, binary counter stages, and integer divider error.

InputFrequency / Value

OutputImpedance / Frequency

PurposeCalculate setup margin, hold margin, maximum theoretical clock frequency, clock skew effects, and synchronous timing path budgets.

InputFrequency / Value

OutputImpedance / Frequency

PurposeCheck digital logic-level compatibility using VOH, VOL, VIH, VIL, HIGH and LOW noise margins, bidirectional thresholds, and open-drain pull-up logic.

InputEngineering parameters

OutputCalculated result