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Digital Timing Calculator

Calculate setup margin, hold margin, maximum theoretical clock frequency, timing path delay and clock skew effects for a simplified synchronous register-to-register path.

This calculator is an educational engineering model for launch flip-flop to combinational logic to capture flip-flop timing. It does not replace Vivado Timing Analysis, Quartus Timing Analyzer, PrimeTime, Tempus or signoff static timing analysis.

Engineering tool

Digital Timing Calculator

Analyze simplified synchronous digital timing paths with setup margin, hold margin, maximum theoretical clock frequency, clock skew and clock uncertainty.

Calculator mode

Parameter panel

Clock definition for setup analysis. Frequency and period conversion reuses the shared ECParts unit conversion utility.

Maximum launch flip-flop clock-to-Q delay. Setup analysis uses maximum delay.

Maximum combinational logic and routing delay.

Capture flip-flop setup time requirement.

Simplified setup timing uncertainty or margin reserve.

Minimum launch flip-flop clock-to-Q delay. Hold analysis uses minimum delay.

Minimum combinational logic and routing delay.

Capture flip-flop hold time requirement.

Simplified hold uncertainty. It is separate from setup uncertainty.

Tskew = capture clock arrival - launch clock arrival. Positive skew helps setup and hurts hold in this model.

Result console

Worst Margin
700ps
Setup Status
Setup Met
Setup Margin
1.5ns
Hold Status
Hold Met
Hold Margin
700ps
Maximum Theoretical Frequency
117.647059MHz
Minimum Logic Delay Requirement
100ps
Timing Summary
Setup Met; Hold Met. Hold violations are minimum-delay problems and are not automatically repaired by lowering clock frequency.

Setup Analysis

Setup Margin
1.5ns
Setup Status
Setup Met
Clock Period
10ns
Clock Frequency
100MHz
Data Arrival Time
7ns
Required Clock Period
8.5ns
Maximum Logic Delay Allowed
7.5ns
Formula
Msetup = Tclock - (Tcq,max + Tlogic,max + Tsetup + Tuncertainty - Tskew)

Hold Analysis

Hold Margin
700ps
Hold Status
Hold Met
Earliest Data Arrival
1.3ns
Required Hold Boundary
600ps
Required Minimum Logic Delay
100ps
Formula
Mhold = Tcq,min + Tlogic,min - Thold - Tskew - Tuncertainty,hold

Skew convention: Tskew = capture clock arrival - launch clock arrival. Positive skew helps setup timing and hurts hold timing in this simplified register-to-register model.

Formula reference

Digital Timing Formulas

This calculator uses Tskew = capture clock arrival - launch clock arrival. Positive skew helps setup and hurts hold in this simplified model.

Trequired = Tcq,max + Tlogic,max + Tsetup + Tuncertainty - TskewMsetup = Tclock - TrequiredTlogic,max,allowed = Tclock - Tcq,max - Tsetup - Tuncertainty + TskewMhold = Tcq,min + Tlogic,min - Thold - Tskew - Tuncertainty,holdTlogic,min,required = Thold + Tskew + Tuncertainty,hold - Tcq,minfmax = 1 / (Tcq,max + Tlogic,max + Tsetup + Tuncertainty - Tskew)Tclock = 1 / fclock

Variable definitions

Tclock
clock period
Tcq,max
maximum clock-to-Q delay for setup analysis
Tcq,min
minimum clock-to-Q delay for hold analysis
Tlogic,max
maximum combinational logic and routing delay
Tlogic,min
minimum combinational logic and routing delay
Tsetup
capture flip-flop setup time
Thold
capture flip-flop hold time
Tskew
capture clock arrival minus launch clock arrival
Tuncertainty
simplified clock uncertainty or margin reserve

Worked Examples

Setup Pass

Clock = 10 ns, Tcq,max = 1 ns, logic,max = 6 ns, setup = 1 ns, uncertainty = 0.5 ns, skew = 0 -> required = 8.5 ns and margin = 1.5 ns.

Setup Violation

Clock = 8 ns with the same 8.5 ns required period -> setup margin = -0.5 ns.

Positive Setup Skew

With +1 ns skew, required period becomes 7.5 ns and setup margin at a 10 ns clock becomes 2.5 ns.

Negative Setup Skew

With -1 ns skew, required period becomes 9.5 ns and setup margin at a 10 ns clock becomes 0.5 ns.

Hold Pass

Tcq,min = 0.5 ns, logic,min = 0.8 ns, hold = 0.5 ns, uncertainty = 0.1 ns, skew = 0 -> hold margin = 0.7 ns.

Hold Violation

Tcq,min = 0.2 ns, logic,min = 0.1 ns, hold = 0.5 ns, uncertainty = 0, skew = 0 -> hold margin = -0.2 ns.

Positive Skew Hurts Hold

Using the hold-pass path with +0.5 ns skew reduces hold margin from 0.7 ns to 0.2 ns.

Maximum Frequency

Tcq,max = 1 ns, logic,max = 6 ns, setup = 1 ns, uncertainty = 0.5 ns -> Tmin = 8.5 ns and fmax ≈ 117.647 MHz.

Zero Logic Delay

A zero-delay simplified setup path can be calculated, but real devices still include routing, clock-to-Q, setup, skew and uncertainty.

Required Logic Budget

At 100 MHz, Tclock = 10 ns. With Tcq = 1 ns, setup = 1 ns and uncertainty = 0.5 ns, maximum logic delay is 7.5 ns.

Hold Minimum Logic Requirement

Thold = 1 ns, skew = 0.2 ns, uncertainty = 0.1 ns and Tcq,min = 0.5 ns require 0.8 ns minimum logic delay.

Compare Paths

If Path A requires 8 ns and Path B requires 9 ns, Path B is the critical setup path in that comparison.

Frequency / Period

100 MHz corresponds to a 10 ns clock period using the shared frequency-period utility.

1 GHz Reference

1 GHz corresponds to a 1 ns clock period.

Clock Uncertainty Increase

Increasing setup uncertainty reduces setup margin; increasing hold uncertainty reduces hold margin.

BigInt Not Required

DIG-011 timing math uses finite SI seconds. It does not depend on binary BigInt arithmetic used by fixed-width digital number tools.

Engineering Notes

  • The V1 timing model is a simplified launch flip-flop to combinational logic to capture flip-flop path.
  • Setup time defines how long input data must be stable before the active capture edge.
  • Hold time defines how long input data must remain stable after the capture edge.
  • Clock-to-Q delay describes how quickly the launching flip-flop changes Q after its active edge.
  • Setup analysis uses maximum clock-to-Q and maximum data-path delay.
  • Hold analysis uses minimum clock-to-Q and minimum data-path delay.
  • Maximum clock frequency is generally constrained by the longest setup-critical path.
  • Slower clock frequency may improve setup margin.
  • Slower clock frequency does not automatically repair a hold violation.
  • This calculator defines skew as capture clock arrival minus launch clock arrival.
  • Positive capture skew helps setup under this calculator's convention.
  • Positive capture skew hurts hold under the same convention.
  • Clock uncertainty reduces available timing margin.
  • Combinational delay includes logic and routing in real hardware.
  • FPGA routing delay may be as important as logic delay.
  • A path meeting this simplified calculator does not guarantee device timing closure.
  • Real STA uses device-specific libraries, routing data, clock constraints and PVT corners.
  • This calculator does not model metastability probability.
  • CDC paths require dedicated clock-domain-crossing methodology.
  • Derived clocks from a frequency divider may require proper timing constraints.
  • Counter timing can be affected by ripple versus synchronous implementation.

Common Mistakes

  • Confusing setup time with hold time.
  • Using minimum delay for setup analysis. Setup should use maximum delay.
  • Using maximum delay for hold analysis. Hold should use minimum delay.
  • Assuming lowering frequency fixes every hold violation.
  • Ignoring clock-to-Q delay.
  • Ignoring routing and combinational delay.
  • Ignoring clock skew.
  • Using an unclear clock-skew sign convention.
  • Ignoring clock uncertainty.
  • Treating positive margin as an absolute hardware guarantee.
  • Treating frequency-period conversion as full timing analysis.
  • Replacing FPGA or ASIC STA with a simple logic-level calculator.
  • Ignoring min/max delay differences.
  • Assuming the largest logic-only delay is always the critical path.

Support reference

FAQ

What is setup time?

Setup time is the minimum time that input data must be stable before the active capture clock edge so a flip-flop can sample the value reliably.

What is hold time?

Hold time is the minimum time that input data must remain stable after the active capture clock edge. Hold analysis uses minimum path delay, not maximum delay.

How do I calculate setup margin?

Using this calculator's skew convention, setup margin is Msetup = Tclock - (Tcq,max + Tlogic,max + Tsetup + Tuncertainty - Tskew).

How do I calculate hold margin?

Hold margin is Mhold = Tcq,min + Tlogic,min - Thold - Tskew - Tuncertainty,hold. A negative value indicates a simplified hold violation.

How do I calculate maximum clock frequency?

The maximum theoretical clock frequency is fmax = 1 / Tmin, where Tmin = Tcq,max + Tlogic,max + Tsetup + Tuncertainty - Tskew.

What is clock-to-Q delay?

Clock-to-Q delay is the time from a launch flip-flop clock edge to the point where its Q output changes. Setup uses Tcq,max, while hold uses Tcq,min.

What is clock skew?

This calculator defines skew as capture clock arrival minus launch clock arrival. Positive skew means the capture clock arrives later.

Does positive clock skew help setup timing?

Yes, under this calculator's convention positive capture skew increases available setup time, so it reduces the required clock period.

Why can positive skew hurt hold timing?

Positive capture skew moves the capture edge later relative to the launch edge, increasing the hold boundary and reducing hold margin in the simplified model.

Can lowering clock frequency fix a hold violation?

Not automatically. Setup violations often improve with a slower clock, but hold violations are minimum-delay problems near the same capture edge.

What is a critical path?

For setup comparison, the critical setup path is the path with the larger required clock period. For hold comparison, the more hold-critical path has the smaller hold margin.

How is this different from static timing analysis?

This is a basic synchronous timing model. It does not replace Vivado, Quartus, PrimeTime, Tempus, device timing libraries, routed delays, PVT corners, clock constraints, or signoff STA.

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Related Engineering Guides

Planned Guide

Setup and Hold Time Explained

Planned Guide

Clock-to-Q Delay

Planned Guide

How to Calculate Maximum Clock Frequency

Planned Guide

Clock Skew in Digital Systems

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Critical Paths in Synchronous Logic

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Static Timing Analysis Basics