Flip-Flop Calculator & Truth Table
Analyze ideal edge-triggered SR, JK, D and T flip-flop behavior, including next states, characteristic tables, excitation tables and clock-edge sequence transitions.
DIG-008 focuses on sequential state logic. It does not model propagation delay, setup or hold timing, metastability, HDL simulation, transistor-level latch behavior, clock skew or asynchronous set/reset timing.
Engineering tool
Flip-Flop Calculator & Truth Table
Analyze SR, JK, D, and T flip-flop next states, characteristic tables, excitation tables, state transitions, comparisons, and ideal clock-edge sequences.
Parameter panel
V1 models ideal edge-triggered synchronous behavior.
Current state Q(n) before the active clock edge.
Set-like JK input.
Reset-like JK input. J=K=1 toggles.
Result console
- Next State Q(n+1)
- 1
- Flip-Flop Type
- JK
- Current State Q(n)
- 0
- Inputs
- J=1, K=1
- Operation
- toggle
- Validity
- Valid
- Transition
- 0 -> 1
- Equation
- Q(n+1) = J·Q(n)' + K'·Q(n)
Characteristic equation: Q(n+1) = J·Q(n)' + K'·Q(n)
V1 models ideal synchronous state transitions at active clock edges. Setup time, hold time, clock-to-Q delay, metastability, asynchronous preset, and asynchronous clear are not modeled.
Formula reference
Flip-Flop Characteristic Equations
Q(n) is the current state and Q(n+1) is the next state after the active clock edge.
SR: Q(n+1) = S + Q(n)·R' for valid inputsJK: Q(n+1) = J·Q(n)' + K'·Q(n)D: Q(n+1) = DT: Q(n+1) = T XOR Q(n)Variable definitions
- S
- set input
- R
- reset input
- J and K
- JK control inputs
- D
- data input
- T
- toggle input
- X
- Don't Care in excitation tables
- SR S
- R=1 = invalid / forbidden in this calculator
Worked Examples
SR Hold
S=0, R=0, Q=1 gives Q(n+1)=1.
SR Set
S=1, R=0, Q=0 gives Q(n+1)=1.
SR Reset
S=0, R=1, Q=1 gives Q(n+1)=0.
SR Invalid
S=1, R=1 is invalid / forbidden and no fake next Q is returned.
JK Hold
J=0, K=0, Q=1 gives Q(n+1)=1.
JK Reset
J=0, K=1, Q=1 gives Q(n+1)=0.
JK Set
J=1, K=0, Q=0 gives Q(n+1)=1.
JK Toggle
J=1, K=1 toggles Q, so 0 becomes 1 and 1 becomes 0.
D Load 1
D=1, Q=0 gives Q(n+1)=1.
D Load 0
D=0, Q=1 gives Q(n+1)=0.
T Hold
T=0, Q=1 gives Q(n+1)=1.
T Toggle
T=1, Q=1 gives Q(n+1)=0.
JK Excitation 0 to 1
Q 0 -> 1 requires J=1, K=X.
T Excitation 1 to 0
Q 1 -> 0 requires T=1.
T Sequence
Initial Q=0 with T inputs 1,1,1,1 gives 0->1->0->1->0.
D Sequence
Initial Q=0 with D inputs 1,1,0,1 gives Q states 1,1,0,1.
Engineering Notes
- Flip-flops store one bit of state.
- Sequential logic depends on previous state as well as current inputs.
- Q(n) is the current state and Q(n+1) is the next state after the active clock edge.
- D flip-flops copy D to Q at the active edge in the ideal model.
- T flip-flops toggle when T=1.
- JK flip-flops define J=K=1 as toggle and avoid the basic SR forbidden input.
- SR S=R=1 is treated as invalid / forbidden in this calculator.
- Excitation tables identify inputs needed for a desired state transition.
- X means Don't Care, not an unknown hardware voltage.
- Real flip-flops have setup, hold and clock-to-Q timing not modeled here.
- Clock polarity and edge sensitivity depend on the actual device.
- Sequence simulation is ideal state logic, not waveform simulation.
Common Mistakes
- Confusing latch and flip-flop behavior.
- Mixing up current Q and next Q.
- Forgetting that JK 11 means toggle.
- Treating SR 11 as a normal valid state.
- Assuming D input is ANDed or ORed with current Q.
- Assuming T=1 always outputs 1.
- Confusing characteristic tables with excitation tables.
- Treating Don't Care X as logic 0.
- Ignoring the active clock edge.
- Assuming state logic includes setup and hold timing.
- Expecting the sequence calculator to model metastability.
- Ignoring asynchronous preset or clear polarity in real ICs.
Support reference
FAQ
What is a flip-flop?
A flip-flop is a clocked sequential logic element that stores one bit of state.
What is the difference between a latch and a flip-flop?
A latch is level-sensitive, while a flip-flop is normally edge-triggered. This calculator models ideal edge-triggered flip-flop behavior.
How does an SR flip-flop work?
SR inputs can hold, set or reset the state. S=R=1 is treated as invalid / forbidden in this calculator.
Why is S=R=1 invalid for an SR flip-flop?
S=R=1 attempts to set and reset at the same time. Physical behavior depends on implementation, so V1 marks it invalid.
How does a JK flip-flop work?
A JK flip-flop behaves like SR for 00, 01 and 10, but defines J=K=1 as toggle.
What happens when J=K=1?
The JK flip-flop toggles, so Q(n+1) becomes the inverse of Q(n).
What does a D flip-flop do?
A D flip-flop loads D into Q at the active clock edge in the ideal logic model.
How does a T flip-flop toggle?
When T=1, the next state is the inverse of the current state. When T=0, the state holds.
What is a characteristic table?
A characteristic table lists next state Q(n+1) for each input combination and current state.
What is an excitation table?
An excitation table solves the reverse problem: which inputs are needed to produce a desired state transition.
What does X mean in a flip-flop excitation table?
X means Don't Care. It is not an unknown voltage, and safe valid input choices still matter.
Does this calculator include setup and hold time?
No. Setup time, hold time, clock-to-Q delay and metastability are timing topics handled separately from ideal state logic.
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Open calculatorRelated Engineering Guides
Planned Guide
Flip-Flops Explained
Planned Guide
SR vs JK vs D vs T Flip-Flops
Planned Guide
Flip-Flop Characteristic Tables
Planned Guide
Flip-Flop Excitation Tables
Planned Guide
Sequential Logic Basics
Planned Guide
Registers and Counters
Planned Guide