Pierce Crystal Oscillator Calculator
Calculate Pierce crystal oscillator load capacitance, external load capacitors, stray capacitance, load error, measured ppm, and crystal specification ranges. The calculator is focused on MCU and logic-IC crystal oscillator load design.
This page does not claim startup margin from capacitance alone. Startup depends on crystal ESR, oscillator negative resistance, bias, drive level, PCB layout, and device-specific guidance.
Engineering tool
Pierce Crystal Oscillator Calculator
Analyze Pierce crystal oscillator load capacitance, external capacitors, stray capacitance, ppm error, and crystal specification ranges.
Mode
Parameter panel
Optional for analyze mode; required for measured ppm mode.
Result console
- Effective Load Capacitance
- 12 pF
- External Series C
- 9 pF
- Load Error
- -0.5 pF
- Load Error
- -4%
- C1:C2 Ratio
- 1
- Status
- Underloaded
Load-capacitance error is not converted to exact ppm; crystal pulling requires equivalent-circuit parameters and manufacturer data.
Correct load capacitance does not guarantee startup; ESR, negative resistance, bias, drive level, PCB loss, and device circuit matter.
Pierce Formula Audit
- Adopted Load Model
- Common Pierce approximation: CL = (C1C2)/(C1 + C2) + Cstray.
- C1 Definition
- External load capacitor from one crystal terminal to ground.
- C2 Definition
- External load capacitor from the other crystal terminal to ground.
- Stray Capacitance
- Estimated MCU pin, PCB, package, routing, and miscellaneous capacitance.
- Effective CL Formula
- CL is not C1 + C2; equal capacitors contribute C/2 before adding Cstray.
- Symmetric Solution
- C1 = C2 = 2(CLtarget - Cstray), requiring CLtarget > Cstray.
- Asymmetric Solver
- Cother = Cseries Cknown / (Cknown - Cseries), requiring Cknown > Cseries.
- Required Stray Solver
- Cstray = CLtarget - (C1C2)/(C1 + C2), requiring non-negative result.
- Load Error
- Delta CL = CLeffective - CLspec.
- PPM Formula
- Measured ppm = (fmeasured - fnominal)/fnominal × 10^6.
- Crystal Pulling Boundary
- CL error alone is not a universal exact ppm-pulling model.
- ESR / Startup Boundary
- Startup depends on crystal ESR and oscillator negative resistance.
- Drive-Level Boundary
- Drive-level power is referenced but not calculated in this V1 model.
- Formula Used
- 12 pF effective CL.
Formula reference
Pierce Crystal Load Formulas
Pierce load capacitance is the series contribution of C1 and C2 plus estimated stray capacitance.
Cseries = C1C2 / (C1 + C2)CL = Cseries + CstrayFor C1 = C2 = C: Cseries = C / 2C = 2(CLtarget - Cstray)C2 = CseriesC1 / (C1 - Cseries)Cstray = CLtarget - Cseriesppm = (fmeasured - fnominal) / fnominal × 10^6Δf = fnominal × ppm × 10^-6Variable definitions
- C1
- external load capacitor on one crystal terminal
- C2
- external load capacitor on the other terminal
- Cstray
- MCU pin, PCB, package, and routing capacitance
- CL
- effective load capacitance seen by the crystal
- fmeasured
- measured oscillator frequency
- fnominal
- nominal crystal frequency
Pierce Crystal Formula Audit
| Adopted Load Model | Common Pierce approximation with C1 and C2 from crystal pins to ground plus lumped Cstray. |
|---|---|
| C1 Definition | External load capacitor from one crystal terminal to ground. |
| C2 Definition | External load capacitor from the other crystal terminal to ground. |
| Stray Capacitance | MCU pin, PCB, package, routing, and miscellaneous capacitance approximation. |
| Effective CL Formula | CL = (C1C2)/(C1 + C2) + Cstray. |
| Symmetric Solution | C1 = C2 = 2(CLtarget - Cstray), requiring CLtarget > Cstray. |
| Asymmetric C1 Solver | C1 = Cseries C2/(C2 - Cseries), requiring C2 > Cseries. |
| Asymmetric C2 Solver | C2 = Cseries C1/(C1 - Cseries), requiring C1 > Cseries. |
| Required Stray Solver | Cstray = CLtarget - (C1C2)/(C1 + C2), requiring non-negative result. |
| Load Error | Delta CL = CLeffective - CLspec. |
| PPM Formula | ppm = (fmeasured - fnominal)/fnominal × 10^6. |
| Crystal Pulling Boundary | Load error alone is not converted into exact crystal ppm pulling. |
| ESR / Startup Boundary | Startup depends on ESR, negative resistance, bias, drive level, and PCB loss. |
| Drive-Level Boundary | Drive level is referenced but not calculated. |
Worked Examples
Symmetric design
Known: CLspec = 12.5 pF, Cstray = 2 pF
C1 = C2 = 21 pF.
Effective load
Known: C1 = C2 = 18 pF, Cstray = 3 pF
CL = 9 pF + 3 pF = 12 pF.
Asymmetric load
Known: C1 = 18 pF, C2 = 22 pF, Cstray = 2 pF
Cseries = 9.9 pF, CL = 11.9 pF.
Solve C2
Known: CL = 12.5 pF, stray = 2.5 pF, C1 = 20 pF
Cseries target = 10 pF, C2 = 20 pF.
Near singular
Known: Known capacitor equals Cseries
No finite positive solution is returned.
Invalid symmetric
Known: CLtarget <= Cstray
The symmetric solver rejects negative external capacitors.
Required stray
Known: CLtarget = 12 pF, C1 = C2 = 20 pF
Required Cstray = 2 pF.
Negative stray
Known: External series load already exceeds target
The required stray solver rejects the target.
Positive ppm
Known: 16 MHz measured as 16.000160 MHz
Error = +10 ppm.
Negative ppm
Known: 10 MHz measured as 9.999900 MHz
Error = -10 ppm.
Frequency range
Known: 16 MHz ±20 ppm
Deviation = ±320 Hz.
Stray increment
Known: Fixed C1/C2 with +1 pF stray
Effective CL increases by 1 pF.
Equal capacitor relation
Known: C1 = C2 = C
External series contribution is C/2.
Capacitance units
Known: 1000 pF = 1 nF
Equivalent inputs produce the same CL.
Frequency units
Known: 1 MHz = 1000 kHz
PPM calculations match.
Symmetric round trip
Known: Solve equal C1/C2 then analyze
Analyzer recovers target CL.
Asymmetric round trip
Known: Solve C1 or C2 then analyze
Analyzer recovers target CL.
PPM range round trip
Known: ppm -> frequency deviation
Frequency limits match nominal ± deviation.
Engineering Notes
Pierce oscillator
Pierce is one of the most common crystal oscillator topologies used with MCUs and logic ICs.
Load capacitance
External capacitors and parasitics determine the effective load seen by the crystal.
Equal capacitors
Equal external capacitors are approximately 2(CL - Cstray), not CL.
Stray capacitance
MCU oscillator pins often contribute capacitance that must be included in Cstray.
Load resonance
Manufacturer frequency is usually specified at a load capacitance condition; do not confuse it with pure series resonance.
Crystal pulling
Load-capacitance error cannot generally be converted to exact ppm without crystal equivalent-circuit data.
ESR
Crystal ESR must be overcome by oscillator negative resistance for reliable startup.
Drive level
Excess drive can shift frequency, increase aging, or damage the crystal.
Probe loading
Oscilloscope probes can add capacitance and disturb or stop oscillation.
Layout
Short traces, clean ground, low noise, and datasheet layout guidance matter.
Tolerance specs
Tolerance, temperature stability, and aging are separate crystal specifications.
Validation
Critical startup should be verified on hardware across voltage and temperature.
Common Mistakes
- Using CL = C1 + C2.
- Forgetting stray capacitance.
- Setting equal capacitors directly equal to CL.
- Returning positive capacitors when Cstray >= CL.
- Converting CL error directly to exact ppm.
- Assuming correct CL guarantees startup.
- Ignoring crystal ESR.
- Ignoring MCU pin capacitance.
- Ignoring oscilloscope probe loading.
- Ignoring drive level.
- Confusing series resonance with load resonance.
- Treating tolerance, temperature stability, and aging as the same specification.
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Support reference
FAQ
What is a Pierce crystal oscillator?
A Pierce crystal oscillator is a common crystal oscillator topology used in MCUs and logic ICs. It uses a crystal, an inverting amplifier, and load capacitors.
How do I calculate crystal load capacitance?
Use the common approximation CL = (C1C2)/(C1 + C2) + Cstray, where Cstray includes MCU pin, PCB, package, and routing capacitance.
How do I choose C1 and C2?
For equal capacitors, choose C1 = C2 = 2(CLtarget - Cstray), requiring the target CL to be greater than the estimated stray capacitance.
Why are equal load capacitors approximately twice the required external series load?
Two equal capacitors C in series contribute C/2, so each external capacitor must be about twice the desired external series capacitance.
What is stray capacitance?
Stray capacitance is the lumped estimate of MCU pin capacitance, crystal package capacitance, PCB pads, routing, solder mask, and nearby copper.
How much PCB stray capacitance should I assume?
It depends on package, layout, ground, and MCU pins. Many early estimates use a few picofarads, then refine with datasheets and measurement.
What happens if the load capacitance is too high?
The crystal is overloaded relative to its specified CL, which can shift frequency and may affect startup depending on the oscillator circuit.
What happens if it is too low?
The crystal is underloaded relative to its specified CL, which can shift frequency in the opposite direction and alter oscillator margin.
Can I calculate crystal frequency error from load capacitance alone?
Not generally. Accurate pulling requires crystal equivalent-circuit data such as motional capacitance, shunt capacitance, and manufacturer model.
How do I calculate frequency error in ppm?
If measured frequency is known, ppm = (fmeasured - fnominal)/fnominal × 10^6.
What is crystal ESR?
ESR is the equivalent series resistance of the crystal at resonance. Oscillator startup depends on the amplifier providing enough negative resistance margin over ESR.
What is negative resistance in a Pierce oscillator?
Negative resistance is the small-signal energy supplied by the oscillator amplifier to overcome crystal ESR and circuit losses. This V1 calculator does not compute it.
Why can an oscilloscope probe stop a crystal oscillator?
Probe capacitance and resistance can change CL, load the node, reduce loop gain, and disturb or stop oscillation.
What is crystal drive level?
Drive level is the power dissipated in the crystal. Excessive drive can shift frequency, increase aging, damage the crystal, or reduce reliability.
What is the difference between crystal tolerance, temperature stability, and aging?
Tolerance is initial frequency error, temperature stability is drift over temperature, and aging is long-term drift over time.