PCB Via Current Capacity and Thermal Design Guide

Introduction

High-current PCB routing is rarely just a wide trace. A complete path may run through a trace, pad, via barrel, internal plane, another via, connector, and load. The via can become a resistance bottleneck, voltage-drop source, thermal hotspot, or current-density hotspot if it is treated as an ideal zero-ohm layer transition.

This guide focuses on vias and via arrays. For trace width, copper thickness, temperature rise, and voltage-drop fundamentals, read Understanding PCB Trace Width, Current Capacity and Temperature Rise.

What Is a PCB Via?

A PCB via is a plated hole that connects copper on different PCB layers. The current path is not the empty hole; it is the copper barrel plated around the wall of the hole. A via also includes pads, annular rings, and the connection into traces or planes.

Common via types include through vias, blind vias, buried vias, and microvias. This article focuses on vias used for power current and thermal transfer. Signal vias and controlled-impedance vias have additional high-frequency and signal-integrity concerns.

Via Geometry and Barrel Area

The key dimensions are finished hole diameter, drill diameter, pad diameter, plating thickness, via length, and board thickness. Finished hole diameter is different from drill diameter because plating changes the final hole size. High-current work should use the fabricator's finished-hole and minimum plating specification.

Via Resistance, Voltage Drop, and Power Loss

A via barrel is a short copper conductor. Longer barrels, smaller diameters, and thinner plating increase resistance. That resistance may look small, but high current can still create measurable voltage drop and local heat.

The ECParts Via Current Calculator uses copper resistivity 1.724 × 10⁻⁸ Ω·m and the thin-wall barrel approximation. It also reports current density in A/mm² as a screening metric, but current density is not a universal pass/fail rule for all boards.

For power background, see Understanding Electrical Power and Power Dissipation and Component Power Ratings.

Why Current Capacity Is Not Just Resistance

Theoretical barrel resistance does not grant unlimited current. Via capability also depends on heat dissipation, local copper spreading, pad connection, plating quality, current crowding, temperature rise, reliability target, and fabrication tolerance.

Parallel Vias and Current Sharing

Multiple vias in parallel reduce ideal equivalent resistance and current per via. In ideal math, identical via resistance in parallel gives Rparallel ≈ Rvia / N. Real layouts may not share current equally because current enters from specific directions through finite copper resistance.

Do not treat four vias as exactly four times the safe current in every layout. Via placement, copper geometry, plane connection, current entry and exit points, and thermal coupling all matter.

Via Arrays, Spacing, Aspect Ratio, and Manufacturing

High-current via arrays are often distributed across the full trace width, staggered through copper pours, or placed near power-device pads. A dense cluster in one corner may not solve current crowding across a wide plane transition.

Via spacing is controlled by annular ring, solder mask, plane connectivity, mechanical strength, thermal coupling, and fabricator design-for-manufacturing rules. Avoid universal spacing rules and use the PCB manufacturer's capability data.

Aspect ratio is approximately board thickness divided by drill diameter. High aspect ratio vias can be harder to plate consistently, especially in thick boards with small holes.

Microvias, Blind Vias, Buried Vias, and Filled Vias

Microvias, blind vias, and buried vias can have different lengths, fabrication processes, reliability behavior, and thermal paths from through vias. Do not copy through-via current assumptions directly into every HDI structure.

Filled, capped, and via-in-pad structures are common under QFN, DFN, MOSFET, regulator, LED, and power amplifier packages. Filled vias are not automatically better current conductors: resin-filled vias mainly support assembly, while copper-filled structures depend on the specified fabrication process.

Thermal Vias

Thermal vias conduct heat from a top copper pad or exposed package pad to internal planes or bottom copper. They are common under power MOSFETs, QFN regulators, LEDs, and power amplifiers.

More thermal vias usually improve the vertical barrel path, but the benefit does not increase forever. Pad area, connected planes, package interface, solder, spreading resistance, fill/cap process, and airflow can become the dominant limits.

Electrical Vias vs Thermal Vias

Many power vias perform both electrical and thermal functions. Analyze both goals when the via sits under a power device or in a high-current rail.

Vias in Real Power Circuits

MOSFET power paths often use vias to connect drain, source, and power planes across layers. Check current sharing, resistance, common-source inductance, heat spreading, and the high-current loop. The How to Choose the Right MOSFET guide covers MOSFET selection and thermal context.

In DC-DC converters, vias in high di/dt loops are not only DC resistance elements. They can add parasitic inductance, switching overshoot, and EMI. In motor drivers and H-bridges, use RMS current for heating and peak/stall current for voltage droop and protection review.

High-power LED boards may use vias for both current transfer and heat spreading. LED thermal paths should include package, solder, copper, vias, board, heatsink, and ambient conditions. See How to Choose the Right LED for LED selection context.

How the ECParts PCB Via Calculators Work

The PCB Via Current Calculator uses finished hole diameter, plating thickness, barrel length, number of parallel vias, total current, and allowed temperature rise. It calculates barrel area, current per via, resistance per via, equivalent resistance, voltage drop, power per via, total power loss, current density, and a conservative loading status.

The PCB Thermal Via Calculator uses via count, finished hole diameter, plating thickness, PCB thickness, copper thermal conductivity, power dissipation, and ambient reference temperature. It calculates barrel conductance, per-via thermal resistance, ideal parallel resistance, temperature drop, hot-side temperature, heat per via, and thermal status.

Both calculators are design aids. They do not fully model local current crowding, complex copper geometry, manufacturing variation, 3D thermal spreading, high-frequency parasitics, solder joints, connector losses, or package-to-board thermal interfaces.

Worked Examples

Current-Carrying Via Design Workflow

1. Define continuous, peak, RMS, and pulse current.
2. Select via geometry: finished hole, pad, drill, and plating.
3. Confirm board thickness and via barrel length.
4. Estimate barrel area and via resistance.
5. Calculate voltage drop and I²R loss.
6. Select a preliminary via count.
7. Review current sharing and current entry/exit geometry.
8. Check pads, planes, neck-downs, and thermal reliefs.
9. Review aspect ratio and manufacturer fabrication rules.
10. Validate high-current paths with voltage and temperature measurements.

Thermal Via Design Workflow

1. Identify the heat source and exposed pad or copper area.
2. Connect the source to an appropriate thermal via array.
3. Connect vias to internal or bottom copper planes where possible.
4. Estimate barrel-only thermal resistance as a first approximation.
5. Review spreading resistance, pad area, solder, package, and plane size.
6. Check assembly process requirements such as via fill, cap, and solder stencil.
7. Validate with thermal measurement or simulation for high-power designs.

PCB Via Design Checklist

• Current requirement
• Peak current
• RMS current
• Finished hole diameter
• Drill diameter
• Plating thickness
• Via length
• Board thickness
• Aspect ratio
• Via resistance
• Voltage drop
• I²R loss
• Via count
• Current sharing
• Via spacing
• Pad geometry
• Plane connection
• Thermal relief
• Local temperature
• Thermal function
• Manufacturing limits
• Calculator assumptions
• Prototype validation

Common Via Design Mistakes

• Using one universal amps-per-via rule.
• Ignoring plating thickness and finished fabrication tolerance.
• Ignoring PCB thickness and via barrel length.
• Assuming finished hole diameter is the same as drill diameter.
• Assuming parallel vias share current perfectly.
• Using too few vias at high-current layer transitions.
• Ignoring pad geometry and current crowding.
• Ignoring voltage drop and I²R loss.
• Treating thermal vias and current-carrying vias as identical design problems.
• Assuming filled vias are automatically better conductors.
• Ignoring aspect ratio and manufacturing limits.
• Treating a calculator result as absolute validation.

Practical Engineering Tips

1. Never assign a universal current rating to a via without geometry and thermal context.
2. Confirm finished hole and plating specifications with the PCB manufacturer.
3. Include board thickness when estimating via resistance.
4. Calculate voltage drop in high-current via transitions.
5. Calculate I²R loss, even when resistance looks small.
6. Use multiple vias where appropriate.
7. Do not assume perfect current sharing.
8. Spread via arrays across the current path.
9. Review neck-downs, pads, thermal reliefs, and plane entry points.
10. Distinguish thermal-via goals from electrical-current goals.
11. Check aspect ratio and fabrication limits before final layout.
12. Validate critical high-current paths with measurements.

Summary

PCB via design combines geometry, plating, board thickness, resistance, current, voltage drop, I²R loss, via count, current distribution, thermal path, and manufacturing limits. The core electrical relationships are R = ρL/A, Vdrop = IR, and Ploss = I²R.

The question “how many amps can one via carry?” has no single correct answer outside geometry and thermal context. Use the PCB Via Current Calculator and PCB Thermal Via Calculator for first-pass review, then validate high-current and high-power layouts with manufacturer data and measurements.