PWM Low-Pass Filter Calculator
Use this calculator to estimate PWM-to-voltage behavior through a first-order RC low-pass filter, including average voltage, carrier attenuation, exact steady-state ripple, harmonic components, and settling time.
This page is intentionally different from a generic RC low-pass calculator: carrier attenuation is reported separately from exact PWM ripple because PWM is a non-sinusoidal waveform with harmonics.
Engineering tool
PWM Low-Pass Filter Calculator
Analyze filtered PWM average voltage, first-order RC cutoff, carrier attenuation, exact steady-state ripple, settling time, and harmonic components.
Parameter panel
Result console
- Average Output
- 2.5 V
- Steady-State Vmin
- 2.4375 V
- Steady-State Vmax
- 2.5625 V
- Ripple p-p
- 124.974 mV
- Ripple / Full Scale
- 2.499%
- Ripple / Average
- 4.999%
- PWM / fc Ratio
- 62.8319
- Carrier Attenuation
- 35.9647dB
| Ton | 50 µs | High interval duration |
|---|---|---|
| Toff | 50 µs | Low interval duration |
| High decay a | 0.95122942 | exp(-Ton/tau) |
| Low decay b | 0.95122942 | exp(-Toff/tau) |
| Average invariant | 2.5 V | DC gain is unity; this is not assumed from (Vmin+Vmax)/2 |
| n | Frequency | Input Peak | Filter Gain | Output Peak |
|---|---|---|---|---|
| 1 | 10 kHz | 3.1831 V | 0.015913 | 50.6542 mV |
| 2 | 20 kHz | 0 V | 0.007957 | 0 V |
| 3 | 30 kHz | 1.061 V | 0.005305 | 5.6289 mV |
| 4 | 40 kHz | 0 V | 0.003979 | 0 V |
| 5 | 50 kHz | 636.6198 mV | 0.003183 | 2.0264 mV |
| 6 | 60 kHz | 0 V | 0.002653 | 0 V |
| 7 | 70 kHz | 454.7284 mV | 0.002274 | 1.0339 mV |
| 8 | 80 kHz | 0 V | 0.001989 | 0 V |
| 9 | 90 kHz | 353.6777 mV | 0.001768 | 0.6254 mV |
| 10 | 100 kHz | 0 V | 0.001592 | 0 V |
Formula reference
PWM RC Low-Pass Formulas
The V1 model uses an ideal two-level PWM source, first-order RC low-pass filter, output across the capacitor, and high-impedance load.
VAVG = D x VH + (1 - D) x VLtau = RCfc = 1 / (2πRC)H(jw) = 1 / (1 + jwRC)|H(f)| = 1 / sqrt(1 + (f/fc)^2)Carrier gain dB = 20log10(|H(fPWM)|)Carrier attenuation = -20log10(|H(fPWM)|)a = exp(-Ton/tau), b = exp(-Toff/tau)Vmin = [VL(1-b) + b VH(1-a)] / (1 - ab)Vmax = VH + (Vmin - VH)aVripple_pp = Vmax - VminSettling time = -tau ln(error fraction)An = 2(VH-VL)|sin(nπD)|/(nπ)Variable definitions
- VH
- PWM high voltage
- VL
- PWM low voltage
- D
- duty cycle as a 0 to 1 fraction
- fPWM
- PWM carrier frequency
- R
- series resistance
- C
- shunt capacitance
- tau
- RC
- fc
- first-order cutoff frequency
PWM Low-Pass Formula Audit
| PWM Average Formula | VAVG = D x VH + (1 - D) x VL |
|---|---|
| Duty Convention | UI accepts percent; internal D = duty% / 100. |
| RC Topology | Series R, shunt C, output across capacitor, high-impedance load. |
| Cutoff Formula | fc = 1 / (2πRC) |
| Time Constant | tau = RC |
| Transfer Function | H(jw) = 1 / (1 + jwRC) |
| Carrier Attenuation | Carrier gain is |H(fPWM)|; attenuation is -20log10(|H|). |
| Exact Ripple Model | Periodic charge/discharge recurrence solves steady-state Vmin and Vmax. |
| Steady-State Vmin | [VL(1-b) + b VH(1-a)] / (1 - ab) |
| Steady-State Vmax | VH + (Vmin - VH)a |
| Ripple Definition | Vripple_pp = Vmax - Vmin |
| Average Preservation | Ideal unity-DC-gain RC output average equals PWM input average. |
| Settling Formula | t = -tau ln(error fraction) |
| Harmonic Convention | Peak sinusoidal amplitude An = 2(VH-VL)|sin(nπD)|/(nπ). |
| Load Assumption | High-impedance load; finite load is not modeled in V1. |
| Source Assumption | Ideal PWM source; driver output resistance is not included in V1. |
Worked Examples
5 V, 50%
Known: VH = 5 V, VL = 0 V, D = 50%
VAVG = 2.5 V.
3.3 V, 25%
Known: VH = 3.3 V, VL = 0 V, D = 25%
VAVG = 0.825 V.
Nonzero low level
Known: VH = 5 V, VL = 1 V, D = 25%
VAVG = 2 V.
RC time constant
Known: R = 10 kΩ, C = 100 nF
tau = 1 ms.
RC cutoff
Known: tau = 1 ms
fc = 159.155 Hz.
PWM ratio
Known: fPWM = 10 kHz
fPWM/fc = 62.8319.
Carrier gain
Known: fPWM/fc = 62.8319
|H| = 1/sqrt(1 + ratio²).
Carrier attenuation
Known: 10 kHz PWM through 10 kΩ / 100 nF
Carrier attenuation is about 35.96 dB.
0% duty
Known: D = 0
Output equals VL and ideal ripple is 0.
100% duty
Known: D = 1
Output equals VH and ideal ripple is 0.
Exact ripple
Known: 50% PWM
Vmin and Vmax are solved from RC recurrence, not a sine approximation.
Period recurrence
Known: Steady-state solution
The next-period Vmin returns to the same value.
Average invariant
Known: Periodic RC waveform
The integrated output average equals PWM average.
Ripple design
Known: Target ripple
Minimum RC is solved then verified with the exact model.
Carrier design
Known: 40 dB target
RC is solved so fPWM response is approximately -40 dB.
99% settling
Known: First-order RC
t = 4.60517 tau.
99.9% settling
Known: First-order RC
t = 6.90776 tau.
50% harmonics
Known: D = 50%
Even harmonics cancel in the ideal Fourier model.
Frequency units
Known: 1000 Hz and 1 kHz
Both produce the same carrier response.
Log sweep
Known: 50 points
Rows remain finite, ordered, and bounded.
PWM Average Voltage
Average voltage depends on duty cycle and high/low levels, not only the supply rail.
PWM DAC
Filtered PWM can approximate analog voltage, but ripple, settling, noise, and resolution limit performance.
Carrier Attenuation
Carrier attenuation is filter gain at fPWM and should not be called total ripple.
Exact Ripple
First-order RC ripple follows exponential charge and discharge during each PWM period.
Settling Time
Lower cutoff reduces ripple but slows response to duty-cycle changes.
Harmonics
PWM contains harmonics; duty cycle controls which harmonics are strong or canceled.
Load Effects
Finite load impedance changes DC gain, effective resistance, cutoff, and ripple.
PWM Resolution
PWM frequency and timer resolution often trade off in microcontroller hardware.
Common Mistakes
Support reference
FAQ
How do I convert PWM to an analog voltage?
Use a low-pass filter so the RC network passes the DC average while attenuating the PWM carrier and harmonics.
How do I calculate PWM average voltage?
For high level VH, low level VL, and duty D, VAVG = D x VH + (1 - D) x VL.
How do I choose R and C for a PWM low-pass filter?
Choose R and C from the required ripple, carrier attenuation, settling time, output impedance, and load constraints.
What cutoff frequency should I use for PWM?
The cutoff is usually well below the PWM frequency when low ripple is needed, but very low cutoff makes output settling slower.
How do I calculate PWM ripple?
This calculator uses the exact steady-state first-order RC charge and discharge solution, not just carrier attenuation.
Is PWM carrier attenuation the same as ripple?
No. Carrier attenuation is the filter gain at fPWM. Total ripple depends on the PWM waveform, duty cycle, and harmonics.
How does PWM frequency affect ripple?
For the same RC values, higher PWM frequency generally lowers ripple because the capacitor has less time to charge and discharge each cycle.
How does duty cycle affect ripple?
Duty cycle changes both the average voltage and harmonic content. At ideal 0% or 100% duty, ripple is zero.
How do I reduce PWM output ripple?
Use a lower cutoff, higher PWM frequency, higher-order filter, buffer, or true DAC when the settling trade-off becomes unacceptable.
How do I calculate RC settling time?
For a first-order RC response, t = -tau ln(error fraction). A 99% settling target is about 4.605 tau.
Why does a lower cutoff make the output slower?
Lower cutoff means a larger RC time constant, so the output changes more slowly after duty-cycle updates.
Do I need a second-order filter for PWM?
A second-order filter can provide more carrier rejection for a given response speed, but component tolerance and stability should be checked.
How does load impedance affect a PWM RC filter?
A finite load appears in parallel with the capacitor and changes DC gain, cutoff frequency, and ripple. V1 assumes high load impedance.
When should I use a DAC instead of filtered PWM?
Use a DAC when ripple, settling time, resolution, noise, or update-rate requirements exceed what filtered PWM can meet.
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Engineering Disclaimer
This calculator uses an ideal first-order RC model with ideal PWM high and low levels and high-impedance load. It does not model finite load impedance, PWM driver resistance, capacitor ESR/leakage, op-amp buffers, ADC sampling behavior, EMI, or real microcontroller timer limitations. Validate critical analog outputs with circuit simulation and measurement.