CAN Bus Bit Timing & Baud Rate Calculator
Calculate Classical CAN nominal bit timing from CAN peripheral clock, effective prescaler, time quanta, TSEG values, SJW, target bit rate, and target sample point.
COM-005 focuses on generic nominal CAN bit timing. It does not calculate CAN FD data-phase timing, transceiver propagation simulation, arbitration, message scheduling, bus load, frame transmission time, or MCU-specific register encoding.
Engineering tool
CAN Bus Bit Timing & Baud Rate Calculator
Calculate Classical CAN nominal bit timing, time quantum, bit rate, sample point, prescaler, SJW validation, and timing candidates.
Use the CAN peripheral clock, not necessarily the CPU core clock.
Enter the effective prescaler, not a register-encoded value.
CAN timing summary
500 kbit/s
Valid: Configuration satisfies the calculator's generic CAN timing constraints.
Result console
- Actual CAN bit rate
- 500kbit/s
- Target bit rate
- 500kbit/s
- Bit-rate error
- 0%
- Time quantum
- 125ns
- Total TQ
- 16TQ
- Bit time
- 2µs
- Sample point
- 87.5%
- Sample-point error
- 0percentage points
- Effective BRP
- 6
- TSEG1
- 13TQ
- TSEG2
- 2TQ
- SJW
- 1TQ
- Validation status
- Valid
Result is valid for the calculator's generic Classical CAN nominal timing model.
Formula reference
CAN Bit Timing Formulas
A Classical CAN nominal bit is divided into time quanta. SyncSeg is normally fixed at 1 TQ.
TQ = BRP / fCANNTQ = 1 + TSEG1 + TSEG2NTQ = 1 + PropSeg + PhaseSeg1 + PhaseSeg2Tbit = NTQ × TQBitRate = 1 / Tbit = fCAN / (BRP × NTQ)SamplePoint = (1 + TSEG1) / NTQ × 100%Error% = (Actual - Target) / Target × 100%Variable definitions
- fCAN
- CAN controller peripheral clock
- BRP
- effective baud rate prescaler, not raw register encoding
- TQ
- time quantum
- NTQ
- total time quanta per bit
- SyncSeg
- synchronization segment, usually fixed at 1 TQ
- TSEG1
- segment before the sample point, commonly PropSeg + PhaseSeg1
- TSEG2
- segment after the sample point, commonly PhaseSeg2
- SJW
- synchronization jump width, usually constrained to SJW ≤ TSEG2
Worked Examples
500 kbit/s from 48 MHz
48 MHz, BRP 6, TSEG1 13, TSEG2 2 gives NTQ = 16, TQ = 125 ns, bit time = 2 µs, bit rate = 500 kbit/s, and sample point = 87.5%.
1 Mbit/s from 48 MHz
48 MHz, BRP 3, TSEG1 13, TSEG2 2 gives NTQ = 16 and bit rate = 1 Mbit/s.
250 kbit/s from 48 MHz
48 MHz, BRP 12, TSEG1 13, TSEG2 2 gives bit rate = 250 kbit/s.
500 kbit/s from 16 MHz
16 MHz, BRP 2, TSEG1 13, TSEG2 2 gives NTQ = 16 and bit rate = 500 kbit/s.
125 kbit/s from 16 MHz
16 MHz, BRP 8, TSEG1 13, TSEG2 2 gives bit rate = 125 kbit/s.
75% sample point
TSEG1 = 11 and TSEG2 = 4 gives NTQ = 16 and sample point = (1 + 11) / 16 = 75%.
Detailed timing segments
PropSeg 5, PhaseSeg1 8, and PhaseSeg2 2 gives TSEG1 = 13, NTQ = 16, and sample point = 87.5%.
Bit-rate error
Target 500 kbit/s and actual 495 kbit/s gives error = -1% and absolute error = 1%.
Timing search from 80 MHz
80 MHz, target 500 kbit/s, 87.5% sample point includes BRP 10, NTQ 16, TSEG1 13, TSEG2 2, and 0% bit-rate error.
Compare sample points
Two 500 kbit/s configurations with 75% and 87.5% sample points have equal bit rate and 12.5 percentage-point sample-point difference.
Invalid SJW
TSEG2 = 2 and SJW = 3 is invalid because SJW must be less than or equal to TSEG2.
Reverse prescaler
48 MHz and target TQ 125 ns gives required BRP = 6.
Engineering Notes
- CAN bit time is built from multiple time quanta.
- SyncSeg is normally fixed at 1 TQ.
- TSEG1 is before the sample point and TSEG2 is after it.
- A later sample point is common on longer buses, but 87.5% is not universal.
- Higher Total TQ gives finer sample-point resolution but must fit the controller range.
- SJW is the maximum resynchronization adjustment and should not exceed TSEG2.
- The CAN peripheral clock may differ from the CPU clock.
- Correct bit rate does not guarantee physical bus reliability.
Common Mistakes
- Using the CPU clock instead of the CAN peripheral clock.
- Entering register-encoded BRP instead of effective BRP.
- Forgetting the 1 TQ Sync Segment.
- Calculating Total TQ incorrectly.
- Confusing TSEG1 with PhaseSeg1 only.
- Leaving propagation delay out of the segment allocation.
- Forgetting the SyncSeg term in the sample-point formula.
- Setting SJW greater than TSEG2.
- Optimizing only bit rate while ignoring sample point.
- Assuming 87.5% is mandatory for every CAN network.
- Ignoring oscillator error, transceiver delay, cable length, stubs, topology, and termination.
- Mixing Classical CAN nominal timing with CAN FD data-phase timing.
MCU Register Encoding Reminder
Many controllers encode timing fields as effective value minus one, such as BRP register = Effective BRP - 1, TSEG1 register = Effective TSEG1 - 1, TSEG2 register = Effective TSEG2 - 1, and SJW register = Effective SJW - 1. Not every device is identical, so verify STM32, NXP FlexCAN, Microchip, TI, Bosch M_CAN, or other MCU documentation before writing register values.
Support reference
FAQ
What is CAN bus bit timing?
CAN bus bit timing defines how one nominal CAN bit is divided into time quanta, including the synchronization segment, TSEG1, TSEG2, and the sample point.
How is CAN baud rate calculated?
The nominal CAN bit rate is calculated as BitRate = fCAN / (BRP × NTQ), where BRP is the effective prescaler and NTQ is the total time quanta per bit.
What is a CAN time quantum?
A time quantum is the smallest timing unit used by the CAN controller bit-timing logic. In this calculator, TQ = BRP / fCAN.
What are TSEG1 and TSEG2?
TSEG1 is the time before the sample point after SyncSeg, usually combining propagation and PhaseSeg1. TSEG2 is the time after the sample point.
How is the CAN sample point calculated?
Sample point is calculated as (1 + TSEG1) / NTQ × 100%, because SyncSeg is normally fixed at 1 TQ.
Why is 87.5% a common CAN sample point?
87.5% is often used for lower-speed or longer CAN buses because it samples later in the bit, but it is not the only valid sample point for every network.
What is synchronization jump width?
SJW is the maximum number of time quanta the controller may adjust during resynchronization. A generic rule is SJW ≥ 1 and SJW ≤ TSEG2.
How do I calculate CAN prescaler?
For a target time quantum, use BRP = TQ × fCAN. The effective BRP must be an integer; MCU register fields may use a different encoded value.
Why does my MCU register value differ from the calculated BRP?
Many controllers encode BRP, TSEG1, TSEG2, and SJW as effective value minus one. This calculator uses effective timing values, not raw register encodings.
How much CAN baud-rate error is acceptable?
There is no universal fixed number. Acceptable error depends on controller tolerance, oscillator accuracy, bus topology, propagation delay, and the complete timing budget.
Does CAN bus length affect bit timing?
Yes. Longer cables and transceiver delays affect propagation timing and may require a later sample point, lower bit rate, or different segment allocation.
Can this calculator be used for CAN FD?
It can be used as a reference for the nominal arbitration phase, but V1 does not provide complete CAN FD data-phase timing or transceiver-delay compensation calculations.
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Future Engineering Guide Topics
CAN Bus Bit Timing Explained
In_DevelopmentCAN Time Quantum and Sample Point
In_DevelopmentHow to Calculate CAN Baud Rate
In_DevelopmentCAN Bus Length vs Bit Rate
In_DevelopmentCAN Termination and Physical Layer Basics
In_DevelopmentClassical CAN vs CAN FD Timing
In_DevelopmentEngineering Disclaimer
This calculator provides generic Classical CAN nominal timing estimates. It does not certify ISO compliance, oscillator tolerance, transceiver timing, bus topology, termination, CAN FD data phase, or MCU-specific register configuration. Verify final designs with datasheets, reference manuals, a CAN analyzer, and physical-layer measurements.